1. Technical Field
This disclosure relates to voltage generating circuits that employ a charge pump circuit.
2. Description of the Related Art
Battery-operated portable devices have limited battery voltages, and so they are designed accordingly. However, such portable devices may sometimes require high voltages for driving a liquid crystal display (LCD) or a light-emitting diode (LED). The most common way of obtaining such high voltages or a large current stably is to use a DC/DC converter. DC/DC converters, however, require discrete elements such as coils, which prevents the reduction of implementation area.
To overcome the above problem, a charge pump circuit is often used, which combines a transistor as a charge transfer element and a capacitor as a pumping element.
FIG. 1 shows a Dickson type charge pump circuit that has conventionally been used as an easy way of constructing a charge pump booster circuit (voltage generating circuit). In the Dickson type charge pump shown in FIG. 1, plural diodes 9111, 9112, and 9113 are connected in series between a power supply node 900 and a boosted output node 9103.
To each of the nodes of the diodes 9111, 9112, and 9113, there is connected one end of each of capacitors 9121 and 9122 via capacitive coupling in order to control the potential at the node. The other ends of the capacitors are fed with complementary clocks so that the odd-numbered capacitor and the even-numbered capacitor are driven in opposite phases.
In this way, a voltage increased from the power supply voltage can be outputted at the output node 9103. For the above diodes, diode-connected N channel MOS transistors (hereafter referred to as “NMOS transistors”) are used. The diode-connected NMOS transistors are connected in series.
One disadvantage of this circuit system is said to be that the system is influenced by the forward voltage Vt of the diodes. When an N-stage Dickson type charge pump circuit is used as a booster circuit, an output voltage Vout that is obtained with a power supply voltage VDD is expressed by the following expression:Vout=(N+1)·(VDD−Vt)  (1)where Vt is the forward voltage of the diode.
As shown in Expression (1), due to the influence of a potential drop by the forward voltage Vt of the diode, a power loss of Vt·Iout is caused per diode. Thus, in the N-stage Dickson type charge pump circuit as a whole, power loss that is caused is expressed by:(N+1)·Vt·Iout  (2)
Thus, efficiency is very poor particularly in the case of a heavy load with a large output current (Iout).
The problem has been tackled by various circuit structures. One of the most common techniques is to use a charge transfer switch (which may be hereafter referred to as “CTS”) instead of a diode. A CTS is generally constructed of a MOS transistor. When given a bias voltage above a threshold voltage Vth, the CTS turns on, whereby the drain-source voltage becomes substantially zero, thus eliminating the influence of Vt that has been causing the aforementioned problem in the Dickson type charge pump circuit.
FIG. 2 shows an example of a charge pump circuit disclosed in Japanese Laid-Open Patent Application No. 2005-339658 (hereafter referred to as Patent Document 1), which is constructed according to the above technology, using NMOS transistors. In this charge pump circuit, NMOS transistors 9211, 9212, and 9213 are connected in series between a voltage input node 900 and a voltage output node 9205, forming a charge transfer circuit. To the nodes between the NMOS transistors, one ends of capacitors 9221, 9222, and 9223 are connected. The other ends of the capacitors 9221, 9222, and 9223 are driven by clocks of plural phases. The gate of the NMOS transistor in a particular stage of the charge transfer circuit is driven by the clock having the same phase as that of its drain. The gate is connected to the drain of another NMOS transistor disposed on the voltage output node side.
Thus, the circuit according to Patent Document 1 employs NMOS transistors as charge transfer switches, wherein an a-th node 9201 and an (a+1)th node 9202 are connected by the NMOS transistor 9211, for example. The signal at an (a+2)th node 9203 is used as a gate signal for the NMOS transistor 9211, thus using the transistor as a switch. If a positive bias can be fed to the gate terminal of the NMOS transistor, the influence due to the Vt in Expressions (1) and (2) can be eliminated.
However, the circuit according to Patent Document 1 is disadvantageous as described below with reference to FIGS. 3 and 4.
As shown in FIGS. 3 and 4, plural NMOS transistors 9211, 9212, 9213, . . . are connected in series between the voltage input node 900 and the voltage output node, forming a charge transfer circuit. To the nodes 9201, 9202, 9203 . . . between these NMOS transistors, there are connected one ends of the capacitors 9221, 9222, 9223, . . . . As to the other ends of these capacitors, the odd-numbered capacitors are fed with a first clock, while the even-numbered capacitors are fed with a clock with an opposite phase to the first clock.
When the NMOS transistors 9211, 9212, 9213 . . . are driven by the complementary clocks φ and /φ, the odd-numbered and even-numbered ones of the transistors are turned on alternately, so that a positive charge is transferred from the voltage input node 900 to the voltage output node, thus performing a boosting operation.
In the circuit of FIG. 3, as the complementary clocks, the odd-numbered NMOS transistors are fed with GND clock, while the even-numbered NMOS transistors are fed with the VDD potential. In the example shown in FIG. 4, as the complementary clocks, the odd-numbered NMOS transistors are fed with the VDD clock while the even-numbered NMOS transistors are fed with GND.
In the examples shown in FIGS. 3 and 4, the gate of the first NMOS transistor 9211 is connected to the node 9202 between the source of the adjacent second NMOS transistor 9212 and the drain of the third NMOS transistor 9203. Similarly, the gate of each of the subsequent NMOS transistors is connected to the node between an adjacent transistor and a further adjacent transistor.
In FIGS. 3 and 4, the source of the NMOS transistor 9211, as a first-stage charge transfer switch, is connected to the power supply input node 900. A node 9204 is connected to a subsequent-stage node in the charge pump circuit.
As mentioned above, a charge pump booster circuit performs a boosting operation by controlling the on/off of the switches in synchronism with clock signals.
In FIG. 3, when the other terminal of the capacitor 9221 is fed with GND, the other terminal of the capacitor 9222 with VDD, and the other terminal of the capacitor 9223 with GND potentials, the NMOS transistor 9211 turns on, the NMOS transistor 9222 turns off, and the NMOS transistor 9223 turns on. In this state, the node 9201 should have VDD, the node 9202 should have 3×VDD, and the node 9203 should have 3×VDD potentials. With respect to the potential VDD of the power supply input 900, the signal at the node 9202, which is applied to the gate terminal of the NMOS transistor 9211, is 3×VDD, so that the NMOS transistor 9211 turns on.
However, with regard to the NMOS transistor 9212 that should be in the off-state, the potential at the node 9201 is VDD compared to the signal 3×VDD at the gate terminal. As a result, the NMOS transistor 9212 turns on, thus contradicting the desired alternate turning on/off operations between the odd-numbered and even-numbered transistors.
Referring to FIG. 4, when the other terminal of the capacitor 9221 is fed with VDD, the other terminal of the capacitor 9222 with GND, and the other terminal of the capacitor 9223 with VDD potentials, the NMOS transistor 9211 should turn off, the NMOS transistor 9212 should turn on, and the NMOS transistor 9213 should turn off, so that the node 9201 should have 2×VDD, the node 9202 should have 2×VDD, and the node 9203 should have 4×VDD.
However, in the NMOS transistor 9211 that should be turned off, the signal at the node 9202, which is the signal applied to the gate terminal of the MOS transistor 9211, has 2×VDD compared to the potential VDD at the power supply input 900. As a result, the NMOS transistor 9211 turns on, thereby causing the aforementioned contradiction.
In an actual circuit operation, an inverse current flows toward the power supply via the charge transfer switch, so that the voltage cannot be boosted.
Patent Document 1 also discloses a differential circuit configuration in which the signal at a node with an opposite phase is used as the gate signal for a NMOS transistor, so that the transistor can be used as a switch. This circuit structure, as shown in FIG. 5, includes two lines of charge transfer circuits between which corresponding transfer stages are driven with opposite phases. The first transfer circuit includes a group of capacitors 9421, 9423, and 9425; the second transfer circuit includes a group of capacitors 9422, 9424, and 9426. The gate of an NMOS transistor 9411 in the first transfer circuit is connected to a node 9404 between the source of a corresponding NMOS transistor 9412 and the drain of a NMOS transistor 9414 in the second transfer circuit. The gate of the NMOS transistor 9412 on the second transfer circuit side is connected to a node 9403 between the source of a corresponding NMOS transistor 9411 and the drain of a NMOS transistor 9413 on the first transfer circuit side. Each of the subsequent transfer stages has similar connection relationships.
To the nodes 9403, 9405, and 9407 on the first transfer circuit side, there are connected capacitors 9421, 9423, and 9425, respectively. To the nodes 9404, 9406, and 9408 on the second transfer circuit side, there are connected capacitors 9422, 9424, and 9426, respectively.
FIG. 6 shows an example in which VDD and GND are fed as opposite signals. In this configuration too, there is the contradiction. Specifically, when the terminals of capacitor elements 9421, 9424, and 9425 are fed with VDD potential and the terminals of capacitor elements 9422, 9423, and 9426 are fed with GND potential, desirably the NMOS transistors 9411, 9414, and 9415 turn off and the NMOS transistors 9412, 9413, and 9416 turn on. In this case, the node 9401 should have 2×VDD, the node 9402 should have VDD, the node 9403 should have 2×VDD, the node 9404 should have 3×VDD, the node 9405 should have 4×VDD, and the node 9406 should have 3×VDD.
However, the NMOS transistor 9414, which should turn off, causes an inverse current of charges toward the power supply 900 due to the higher potential at the node 9403 than at the node 9402.
To deal with this problem, Ming-Dou Ker, Shin-Lun Chen, and Chia-Shen Tsai proposes in their paper (“Design of Charge Pump Circuit With Consideration of Gate-Oxide Reliability in Low-Voltage CMOS Processes”, IEEE Journal of Solid-State Circuit Vol. 41, No. 5 May 2006 (hereafter referred to as “Non-Patent Document 1”)) a circuit as shown in FIG. 7. An operation of the circuit will be described with reference to FIG. 8.
As shown in FIG. 7, the circuit includes two lines of charge transfer circuits between which corresponding transfer stages are driven with opposite phases. A first charge transfer circuit includes capacitors 9621 and 9623. A second charge transfer circuit includes capacitors 9622 and 9624. Between nodes 9601 and 9603, there are provided MOS transistors 9613 and 9615. Similarly, between nodes 9602 and 9604, MOS transistors 9614 and 9616 are provided.
The MOS transistors 9613 and 9614 are NMOS transistors; the MOS transistors 9615 and 9616 are P-channel MOS transistors (hereafter referred to as “PMOS transistors”). To an output node 9607, there are connected PMOS transistors 9617 and 9618 to which an output is fed from the respective charge transfer circuits.
The gate of an NMOS transistor 9611 on the first transfer circuit side is connected to the gate of the next-stage NMOS transistor 9613. The gate of the NMOS transistor 9611 is also connected to a node 9602 between a corresponding NMOS transistor 9612 and the NMOS transistor 9614 on the second transfer circuit side. The gate of the NMOS transistor 9612 on the second transfer circuit side is connected to the gate of the next-stage NMOS transistor 9614.
The gate of the NMOS transistor 9612 on the second transfer circuit side is connected to a node 9601 between the corresponding NMOS transistor 9611 and the NMOS transistor 9613 on the first transfer circuit side. Each of the subsequent transfer stages has a similar connection relationship.
To the nodes 9601 and 9603 on the first transfer circuit side, there are connected the capacitors 9621 and 9623, respectively. To the nodes 9602 and 9604 on the second transfer circuit side, there are connected the capacitors 9622 and 9624, respectively.
The other ends of the capacitors 9621 and 9623 and the capacitors 9622 and 9624 are fed with complementary clocks so that the odd-numbered and even-numbered capacitors are driven with opposite phases.
FIG. 8 shows an example in which complementary clocks are provided by VDD and GND. In FIG. 8, when the capacitor elements 9621 and 9624 are fed with VDD, and the capacitor elements 9622 and 9623 with GND, it is necessary that the power supply input 900 and the node 9601 be cut off from each other, the power supply input 900 and the node 9602 be connected, the node 9601 and the node 9605 be connected, the node 9602 and the node 9606 be cut off from each other, the node 9605 and the output terminal 9607 be cut off from each other, and the node 9606 and the output terminal 9607 be connected.
In the circuit according to Patent Document 1 shown in FIG. 6, the inverse current is caused because there is the MOS transistor 9414 alone between the nodes 9402 and 9404. On the other hand, in the circuit according to Non-Patent Document 1 shown in FIG. 8, the PMOS transistor 9614 and the NMOS transistor 9616 are provided between the nodes 9602 and 9606, thereby preventing the inverse current.
How the inverse current can be prevented in the circuit of FIG. 8 is described below.
With regard to the potential relationship between the gate terminal and the drain terminal of PMOS transistor 9614, the potential at the node 9601, which is applied to the gate terminal, is 2×VDD compared to the potential VDD at the node 9602, which is applied to the drain terminal. Thus, the transistor 9614 turns off. Similarly, as regards the NMOS transistor 9616, the potential at the node 9605, which is applied to the gate terminal, is 2×VDD compared to the potential 3×VDD at the node 9606, which is applied to the drain terminal. Thus, the NMOS transistor 9616 turns off.
The PMOS transistor 9614 and the NMOS transistor 9616 never turn on simultaneously no matter what the value of potential V at the node 9604, which is applied to the source terminal of each of the transistors.
This is because the node 9601 and the node 9605, which are connected to the gate terminals of the transistors PMOS 9614 and NMOS 9616, are at the potential 2×VDD. A condition for causing the PMOS transistor 9614 to turn on is given by:V(potential at node 9604)≧2×VDD−Vtp  (3)
Thus, a condition for causing the NMOS transistor 9616 to turn on is given by:V≦2×VDD−Vtn  (4)
Thus, in order for the two transistors to turn on simultaneously, the following condition must be satisfied:2×VDD−Vtp≦V≦2×VDD−Vtn  (5)
However, given that Vtp has a negative value and Vtn has a positive value, Expression (5) does not hold. Thus, no inverse current is caused in the circuit of FIG. 8.
One disadvantage of the circuit structures shown in FIGS. 7 and 8 is that, because the PMOS and NMOS transistors are connected in series in each stage, the number of the MOS transistors that exist in the charge transfer path between the power supply input and the output terminal is large, which increases the power loss due to the potential drop by the drain-source resistance in each MOS transistor.
The power loss by the drain-source resistance in the 2-stage charge pump booster circuit shown in FIG. 8 is expressed by:Iout·(Rch1·Rch2)/(Rch1+Rch2)  (6)where Rch1 and Rch2 each indicate the drain-source resistance of each of the MOS transistors 9611 to 9618 in the on-state, as shown by the following:Rch1=R9611+R9613+R9615+R9617  (7)Rch2=R9612+R9614+R9616+R9618  (8)